The present application is generally directed to error-correcting circuits and methods. More particularly, the present invention is directed to circuits and methods for use in computer memory systems. The present invention also includes computer memory systems incorporating multi-cycle symbol level error correction devices and processes as described herein.
As memory chips and systems have increase in capacity, the error correction and checking mechanisms employed have shifted from bit-oriented to symbol-oriented codes for improved granularity. However, the overhead in terms of circuit complexity for symbol level error correction systems is generally greater than that found in bit-oriented error correction systems. In order to reduce overhead, long error correction coding schemes are employed. However, a longer ECC (error correction code) codeword requires more input/output pins on the ECC chip that handles error correction and detection.
For example, consider an 8 bit per chip memory. If one wishes to employ a single symbol error detection and double symbol error detection (SSC-DSD) coding system, there is a requirement for 24 check bits for data lengths up to 2040 bits. The overhead for a data length of 64 bits would be 24/64=⅜ and the number is reduced to 24/256= 3/32 for data length of 256 bits. However, using single symbol error detection and double symbol error detection codewords having a codeword length of 280 bits with 256 information bits and 24 redundant check bits requires an ECC chip which is able to receive 280 bits. This imposes significant demands on I/O pin requirements relating to getting information onto and out of a memory chip or its corresponding ECC chip.